IDE3465

20-channel charge sensitive preamplifier-shaper circuit with a total of 37 digital logic trigger outputs and one analog multiplexer output for pulse heights. The chip is designed for readout of the P-side of silicon sensors for charged particles using 16 high-gain channels with saturation at 2.6 pC and 4 low gain-channels with saturation at 26 pC. The high-gain preamplifiers are connected to three parallel shapers, one for spectroscopy with peaking time of 1 µs connected to a sample and hold circuit. The remaining two shapers have different gain and are intended for simultaneous discrimination of pulse heights from both low and high input energies. The shaping time is 250 ns and they are connected to discriminators with 8 bit DAC threshold settings. The discriminator outputs are connected to monostables that enables direct FPGA connection of trigger signals. The trigger signals can either be readout channel by channel or via a common trigger-OR output. The low-gain channel preamplifier is connected to two parallell shapers, one for spectroscopy with peaking time of 1 µs connected to a sample and hold circuit and one for pulse height discrimination using a shaper with 250 ns peaking time. The shaper is connected to one discriminator with a 8-bit threshold. The ASIC is radiation hard by design and has been radiation tested using heavy ions.

Publications

• D. Meier, et al., 2013, “Development of an ASIC for charged particle counting with silicon radiation detectors”, Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2013 IEEE (2013), [doi: 10.1109/NSSMIC.2013.6829764]